EDN

System performance analysis of an all programmable SoC block diagram

The performance of an SoC is measured at the device or system level, not at the interface or circuit block level. A primary component that determines performance is how effectively the system ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...