EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
Nature

Carbon-nanotube computer scaled up

For many decades, progress in electronics has been driven by a gradual reduction in the size of silicon transistors (electronic switches). However, this scaling is becoming increasingly difficult and ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
EDN

An introduction to semiconductor technologies for power management – Part 2

N-MOS and P-MOS transistors are analogous respectively to NPN and PNP transistors but their conduction mechanism is based completely on one type of carrier: holes for the PMOS and electrons for the ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
tom's Hardware on MSN

Intel looks beyond silicon, outlines breakthroughs in atomically-thin 2D transistors, chip packaging, and interconnects at IEDM 2024

Today, the Intel Foundry Technology Research team announced technology breakthroughs in 2D transistor technology using beyond ...