IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Circuits-Informed Machine Learning Technique for Blind Open-Loop Digital Calibration of SAR ADC

Abstract: This work presents a supervised machine-learning (ML) approach for blind digital calibration of SAR ADCs without requiring prior knowledge of errors. A 2-layer neural network learns the ...