Electronic Design

Logic Architecture Cuts Mask And Silicon Costs

Based on an improved logic architecture, the ASAP (Area, Speed and Power) family of high-speed metal programmable cells and high-density standard cells significantly reduces mask and silicon costs.
EDN

Virtex 5 architecture: optimized blocks and lots of I/Os

Like the chips in Xilinx Inc.'s Virtex 4 family, each Virtex 5 FPGA will include the logic fabric, blocks of dedicated RAM, dedicated but configurable blocks optimized for DSP algorithms, and lots of ...
Design-Reuse

Xilinx 7 Series FPGAs Slash Power Consumption by 50% and Reach 2 Million Logic Cells on Industry's First Scalable Architecture

Virtex-7, Kintex-7, and Artix-7 Families Deliver Breakthrough Levels of Lower Power, System Performance and Design Productivity to Support New Applications and Markets SAN JOSE, Calif., June 21, 2010- ...
Electronic Design

SmartNIC Architectures: The Future is a Portable Architecture

Development of a programming language for the data plane. The importance of composability for NIC portables. Managing programs and data with the control plane. This is the fifth chapter in our ...